| Bus Architecture | - Data Bus
- Address Bus
- Control Bus
| System of communication pathways for data and control signals | Transfers data and control signals between components |
| Data Paths | - Internal Address Bus
- Internal Data Bus
- Internal Control Bus
| Internal routes for data movement within the CPU | Enables data movement within the processor |
| Registers | - Memory Address Register (MAR)
- Memory Data Register (MDR)
- Accumulator (AC)
- Program Counter (PC)
- Current Instruction Register (CIR)
| Small, high-speed storage units within the CPU | Facilitates rapid data access and manipulation |
| Memory Hierarchy | - Cache Memory
- RAM
- Secondary Storage
| Structured approach to balance speed and storage capacity | Optimizes data access times and storage efficiency |
| Instruction Cycle | - Fetching
- Decoding
- Executing
- Storing
| Process of executing a program's instructions | Fetches, decodes, executes, and stores instructions |
| Pipeline Processing | - | Technique to enhance efficiency by processing multiple instructions simultaneously | Improves CPU utilization and speeds up execution |
| Interrupts and I/O | - | Signals for managing urgent events and I/O operations | Handles interactions with peripheral devices |
| Parallelism | - Multi-core CPUs
- Distributed Systems
| Simultaneous execution of multiple tasks to improve processing speed | Enhances data transmission speed and overall system performance |